(First Prior Art)
FIG. 12 schematically shows a cross-sectional structure of a general conventional power composite integrated semiconductor device J1. In the power composite integrated semiconductor device J1 of FIG. 12, reference numeral 22 represents a power device portion, and reference numeral 23 represents a control circuit portion.
In the power composite integrated semiconductor device J1 of FIG. 12, in order to reduce the ON-resistance of a power device to be combined, it is needed to reduce not only the normalized ON-resistance determined by the structure of the power device, but also the wire resistance of wires 27. Aluminum alloy is generally used as a wire material. However, it is considered that copper having smaller specific resistance is used to reduce the wire resistance.
FIG. 13 is a schematic top view showing an embodiment of a mount style using wire bonding in the conventional general power composite integrated semiconductor device J1.
The power composite integrated semiconductor device J1 shown in FIG. 13 is constituted by a power device portion 200 surrounded by two-dotted chain line and a control circuit portion 204 surrounded by a broken line in FIG. 13 and also a dedicated pad area (reference numerals 24, 25 of FIG. 12) having no function element there under at the peripheral portion. A bonding wire 206 is connected to bonding pads 203 and 205 on the pad area, whereby the power composite integrated semiconductor device J1 is mounted. With respect to this mount style, when the power device portion 200 and the control circuit portion 204 are reduced in area by miniaturization, but the number of bonding pads 203, 205 for input/output is equal to that before the miniaturization, the chip size of the power composite integrated semiconductor device J1 is determined by the number of the bonding pads 203, 205 and the pitch thereof, and thus there occurs a problem that the manufacturing cost of the power composite integrated semiconductor device J1 cannot be reduced.
(Second Prior Art)
FIGS. 14A, 14B show another conventional power composite integration semiconductor device J2. The power composite integrated semiconductor device J2 of FIGS. 14A, B is a flip chip type power composite integrated semiconductor device, wherein FIG. 14A is a schematic diagram showing a cross-sectional structure of the power composite integrated semiconductor device J2, and FIG. 14B shows a state where solder 42 is mounted on an electrode portion.
In the power composite integrated semiconductor device J2 shown in FIGS. 14A, B, copper having lower resistance than aluminum alloy is used as an electrode material of a collector electrode to reduce the ON-resistance of the power device portion 32. In the flip chip type power composite integrated semiconductor device J2, as shown in FIG. 14A, a nickel-plated layer 40 and a gold-plated layer 41 are formed on a copper-plated electrode 39 formed in each of the pad areas 34, 35. Thereafter, as shown in FIG. 14B, the solder 42 is mounted on the electrode portion, and the device is mounted through the solder 42 on a print board or the like.
FIGS. 15A to 15D are cross-sectional views showing the sequential steps of a manufacturing method of the power composite integrated semiconductor device J2 of FIG. 14A.
First, as shown in FIG. 15A, an aluminum wire 72 is formed and protected by silicon nitride film, and then predetermined opening portions are formed.
Subsequently, as shown in FIG. 15B, a barrier layer 74 and a copper seed layer 75 are formed on the surface of a silicon substrate 71, and then resist 75 with electrode forming portions opened is formed.
Subsequently, as shown in FIG. 15C, a copper layer 77, a nickel layer 78 and a gold layer 79 are successively formed with the resist 75 as a mask by plating.
Finally, as shown in FIG. 15D, the resist 75 is removed, and then the whole surface thereof is subjected to etching to remove unnecessary portions of the copper seed layer 75 and barrier layer 74.
The power composite integrated semiconductor device J2 shown in FIG. 14A is thus manufactured.
In the power composite integrated semiconductor device J2 shown in FIGS. 14A, 14B, the electrode formation precision is high. However, it uses the solder 42 for connection in the mounting step and also has a structure that the electrodes are exposed. Therefore, it has a problem that it is impossible to narrow the pad interval in order to keep the insulation performance between the electrodes.
(Third Prior Art)
Recently, there has been-carried out an attempt of reducing the wire resistance of a power device by using the technique of forming copper electrodes in the power composite integrated semiconductor device J2 described above (ISPSD 2001 pp 65-68, non-patent document 1).
FIG. 16 is a schematic diagram showing the cross-sectional structure of another power composite integrated semiconductor device J3 to which the technique of forming the copper electrode in the power composite integrated semiconductor device J2 is applied. Reference numeral 50 in the power composite integrated semiconductor device J3 of FIG. 16 represents polyimide resin film.
In the power composite integrated semiconductor device J3 shown in FIG. 16, a thick-film copper-plated electrode 39 having low resistance is formed on the power electrode portion 32 to reduce the wire resistance of the power device portion 32. Furthermore, a pad area for drawing out the output of the power device is reduced. Therefore, there is achieved a power composite integrated semiconductor device J3 which is low in ON-resistance and reduced in area.
When the power composite integrated semiconductor device J3 is mounted by using generally-used gold wires 42 which can be connected at a narrow interval, it is extremely difficult to directly bond and connect the gold wires 42 to the copper electrodes 39 which are extremely liable to be oxidized because copper oxide film is formed at the bonding time. Therefore, the structure that the nickel-plated layer 40 and the gold-plated layer 41 are laminated on the copper electrodes 39 as shown in FIG. 16 has been hitherto used.
FIG. 17 shows an investigation result of the relationship between the film thickness of the gold-plated layer 41 and the shear force of the bonding connection. As shown in FIG. 17, the shear force indicating the bonding strength is dependent on the gold plating thickness of the uppermost layer, and a gold plating thickness of about 0.5 μm is needed to achieve sufficient strength.
FIG. 18 shows an investigation result of the relationship between the time for which the device of the above electrode structure is left under high-temperature and high-humidity and the tensile strength of bonding connection when the film thickness of the gold-plated layer 41 is varied. As shown in FIG. 18, there is a tendency that the reliability of the bonding connection is lowered as the gold plating thickness is larger.
As the results of FIGS. 17 and 18, in the power composite integrated semiconductor device J3 shown in FIG. 16, it is difficult to establish both the strength and the reliability by the bonding mounting method using the gold wires 42 for the electrodes having the structure that the nickel-plated layer 40 and the gold-plated layer 41 are laminated on the copper electrode 39.
(Fourth Prior Art)
It is estimated that a structure in which gold bonding can be easily performed and the wire resistance of the power device can be reduced can be achieved by increasing the thickness of the aluminum wires 27 of the uppermost layer in the structure shown in FIG. 12. However, when the aluminum wires 27 of the uppermost layer is merely increased, the coating performance of the nitride film for protecting the device to the aluminum wires 27 of the uppermost layer of is deteriorated, resulting in occurrence of a reliability problem of the device. Therefore, the following structure shown in FIG. 19 is analogized.
FIG. 19 is a diagram showing a schematic cross-sectional structure of another conventional power composite integrated semiconductor device J4.
In the power composite integrated semiconductor device J4 shown in FIG. 19, the control circuit portion 45 is completely covered by the nitride film 48. By forming the thick-film aluminum electrode 49 on the power device portion 44, the wire resistance of the power device portion 44, and also the pad area for drawing out the output of the power device can be reduced, and thus the power composite integrated semiconductor device J4 which is low in ON-resistance and saved in area.
FIGS. 20A to 20D are cross-sectional views of each step of a method of manufacturing the power composite integrated semiconductor device J4 of FIG. 19.
First, as shown in FIG. 20A, an aluminum wire 88 is formed and then protected by silicon nitride film 89, and then predetermined opening portions are formed.
Subsequently, as shown in FIG. 20B, an aluminum layer 90 of about 5 μm in thickness serving as electrodes are formed on the surface of the silicon substrate 87. Subsequently, resist 91 having predetermined openings is formed.
Subsequently, as shown in FIG. 20C, the aluminum layer 90 is subjected to patterning through wet etching by using the resist 91 as a mask.
Finally, as shown in FIG. 20D, the resist 91 is removed, and then a polyimide resin layer 94 having predetermined openings is formed.
The power composite integrated semiconductor device J4 shown in FIG. 19 is manufactured as described above.
In the manufacturing method of the power composite integrated semiconductor device J4, the aluminum layer 90 is large in thickness, and thus it can be processed by only isotropic wet etching, so that under-cut 92 shown in FIG. 20C occurs in the etching step. There is a problem that the interval of pad electrodes of the control circuit portion 97 must be particularly increased due to the restriction of the under-cut 92.
Furthermore, FIG. 21 shows Young's modulus and modulus of rigidity of various kinds of electrode materials, and aluminum is lower in young's modulus and modulus of rigidity than the other materials. Therefore, as compared with the copper electrode 39 shown in FIG. 16, the aluminum electrode 93 is more easily deformed when gold wires 95 are directly bonded and connected to the thick-film aluminum electrodes formed on the power device portion 96. Due to the shock based on the deformation of the aluminum electrodes 93 in the bonding step, the crack or the like is liable to occur in the device area below the aluminum electrode 93, particularly the insulating layer formed of silicon nitride film 89.
Furthermore, FIG. 22 shows an investigation result of the thickness of the reaction layer between aluminum and gold when the device is left under high temperature. In a high temperature area from 150° C. to 200° C., the reaction progresses more as the film thickness of aluminum is larger as shown in FIG. 22. Accordingly, when the gold wires 95 are bonded and connected to the aluminum electrodes 93, the high-temperature reliability between the thick-film aluminum electrode 93 and the gold wire 95 is deteriorated by the reaction described above.
(Fifth Prior Art)
A copper wiring structure based on Damascene process used for a fine integrated circuit device is also known as a prior art which makes practical copper wires having excellent gold bonding and low resistance. This structure is disclosed in JP-A-2000-216191 (Patent Document 1), JP-A-2001-15516 (Patent Document 2), JP-A-2001-351940 (Patent Document 3), JP-A-2002-353221 (Patent Document 4), JP-A-2003-152015 (Patent Document 5), and copper wires are embedded in a flattened insulating layer.
FIG. 23 is a diagram schematically showing the cross-sectional structure of an integrated semiconductor device J5 based on the conventional Damascene process.
A bonding pad portion of the integrated semiconductor device J5 shown in FIG. 23 has a structure that aluminum alloy film 58 is laminated through a barrier layer 57 of titanium, titanium nitride film or the like on the surface of the copper wire 55 of about 1 μm in thickness.
FIGS. 24A to 24E are cross-sectional views showing the sequential process steps of a method of manufacturing the integrated semiconductor device J5 of FIG. 23.
Firstly, as shown in FIG. 24A, insulating film 101 is formed on a silicon substrate 100, and the insulating film 101 is flattened by CMP (Chemical Mechanical Polishing).
Subsequently, recesses 102 for forming a wiring pattern are formed as shown in FIG. 24B.
Subsequently, as shown in FIG. 24C, after the barrier layer 103 of tantalum nitride or the like is formed and a copper seed layer is formed, the whole surface of copper 104 is plated.
Subsequently, as shown in FIG. 24D, the copper-plated layer 104 is polished until the surface of the insulating film 101 by CMP to form copper wires 105.
Subsequently, as shown in FIG. 24E, fine multilayered copper wires of about 1 μm in thickness are formed by repeating the forming step of the insulating film 101, the flattening polishing step of the insulating film 101, the forming step of the recesses 102, the film forming step of the barrier layer 103 and the copper seed layer and the whole-surface plating of the copper 104 and the polishing step of the copper-plated layer 104.
Finally, after the aluminum alloy film 114 is laminated through the barrier layer 113 of titanium, titanium nitride or the like and patterning is conducted, silicon nitride film 115 having predetermined openings is formed, thereby bonding gold wires 116.
The integrated semiconductor device J5 shown in FIG. 23 is manufactured as described above.
In order to form a thick-film copper electrode layer by using the method of manufacturing the integrated semiconductor device J5 described above, the wire forming step must be repeated at plural times. Therefore, there is a problem that the device manufacturing cost is increased. In addition, when the copper electrode is broad, the center portion of the copper-plated layer is excessively polished in the polishing step, and thus a phenomenon of thinning of that portion (dishing) occurs. Accordingly, it is cumbersome and difficult to form wide and thick-film copper electrodes.
(Sixth Prior Art)
For example, as disclosed in JP-A-6-204277 (Patent Document 6) and JP-T-2002-532882 (Patent Document 7), it has been recently attempted to carry out a wiring step again after formation of silicon nitride film which means the completion of a wafer process of a semiconductor device and form bonding pads on the circuit (hereinafter referred to as re-wiring pads) in a recent WL-CSP (Wafer Level-Chip Size Package) technique, thereby reducing the outer peripheral area of the semiconductor device in which pads are formed, saving the area of the semiconductor device chip and reducing the cost. In the case of WL-CSP, the mounting step is carried out by using solder, and thus copper electrodes are used as re-wiring pads.
FIG. 25 is a diagram schematically showing the cross-sectional structure of an integrated semiconductor device J6 in which re-wiring pads are formed by using copper.
FIGS. 26A to 26E are cross-sectional views showing the sequential process steps of a method of manufacturing the integrated semiconductor device J6 of FIG. 25.
First, as shown in FIG. 26A, a first polyimide resin layer 122 is formed on a silicon substrate 119 on which an aluminum wire 120 and silicon nitride film 121 are formed. Subsequently, predetermined openings are formed in a polyimide resin layer 122 so as to be connected to the aluminum wire 120, and then a copper seed layer 124 is formed through a barrier layer 123.
Subsequently, as shown in FIG. 26B, a copper-plated layer 125 is formed by using a resist 126 having a predetermined opening as a mask.
Subsequently, as shown in FIG. 26C, after the resist 126 is removed, the whole surface is subjected to etching to remove unnecessary portions of the copper seed layer 124 and barrier layer 123, thereby forming a thick-film copper-plated electrode 127.
Subsequently, as shown in FIG. 26D, imide resin film 128 is coated to cover the copper electrode 127, and an opening pattern is formed by a photolithographic step. Thereafter, a thermally curing treatment is carried out at a temperature from 300 to 380° C.
Accordingly, a crosslinking reaction of the imide resin film 128 progresses, and a second polyimide layer 129 serving as final protection film having excellent heat resistance is formed as shown in FIG. 26E.
Finally, a nickel-plated layer 130 and a gold-plated layer 131 are formed at the opening portion.
The integrated semiconductor device J6 shown in FIG. 25 is manufactured as described above.
The bonding connection performance of the bonding pad portion of the integrated semiconductor device J6 shown in FIG. 25 has the same problem as described with reference to the power composite integrated semiconductor device J3 of FIG. 16 which has the thick-film copper electrode.
Furthermore, in the case of the power composite integrated semiconductor device J3 of FIG. 16, the power composite integrated semiconductor device J4 of FIG. 19 and the integrated semiconductor device J6 of FIG. 25 which have the thick-film electrode structure, thick polyimide film 50 or 69 is used as the final protection film. The thick polyimide film 50, 69 has high coating performance to the thick-film electrode, and it is used as a protector to water and contaminants invading from the external environment and a shock absorber in a plastic packaging step after wire bonding. When the electrodes are copper electrodes in these thick-film electrode structures (FIG. 16 and FIG. 25), nickel-plated layers 40, 67 and gold-plated layers 41, 68 are partially formed to keep the bonding connection performance. On the surfaces and side surfaces of the electrodes other than the above areas, the copper electrodes 39, 66 come into direct contact with the polyimide film 50, 69 serving as the final protection film.
FIG. 27 shows an investigation result of the reactivity (element diffusion) when the device of the structure in which copper and polyimide come into direct contact with each other is held at high temperature of 150 to 200° C. As shown in FIG. 27, a phenomenon that copper diffuses into polyimide occurs due to the high-temperature holding. Accordingly, when the electrode pitch is small, there occurs a time-lapse degradation problem that current leak occurs. This leak phenomenon is accelerated by water or oxygen passing through the polyimide film because the polyimide film cannot perfectly block off external water and oxygen.
FIG. 28 shows an investigation result of the adhesion strength between copper and polyimide after the thermally curing treatment by a long-term leaving test at 200° C. As shown in FIG. 28, there is a problem that the adhesion strength between copper and polyimide after the thermally curing treatment would be deteriorated when they are left for a long time at high temperature. Accordingly, in the case of the copper electrode having a large film thickness of 2 to 6 μm, in addition to the upper surface of the electrode, the area of the electrode side surface coming into contact with the polyimide film is increased, so that the time-lapse degradation problem of the high-temperature reliability such as inter-electrode leakage or exfoliation of polyimide is more remarkable.
[Non-patent Document 1] ISPSD 2001 pp 65-68
[Patent Document 1] JP-A-2000-216191
[Patent Document 2] JP-A-2001-15516
[Patent Document 3] JP-A-2001-351940
[Patent Document 4] JP-A-2002-353221
[Patent Document 5] JP-A-2003-152015
[Patent Document 6] JP-A-6-204277
[Patent Document 7] JP-T-2002-532882